SAVVY-V is the culmination of two years of thinking about and designing a RISC-V development board that is both high-end and flexible. I’m striving for tidy component placement and minimal cable mess, while supporting a wide range of features and use cases:

• physical stacking for clusters via PC/104+ connector
• 2 x 1/10G SFP+ fiber Ethernet, 2 x 1G copper Ethernet
• programmable, flexible clocking via SiLabs clock generator
• resetting (individual and common cluster) and accessible debugging
• option for future expansion boards to support 5G, Wi-Fi 6, SDR, etc.

Render of stack of six SAVVY-V boards

Features & Specifications

• PolarFire SoC (MPFS250T-FCVG484EES)

  • 4 x 64-bit RV64IMAFDC (RV64GC) application processing cores
  • 1 x RV64IMAC monitor core
  • Up to 667 MHz clock (-1 speed grade)
  • -40 °C to 100 °C temperature rating
  • 3.0 CoreMarks®/MHz
  • 2.0 DMIPs/MHz
  • 250K logic elements (4LUT + DFF)

• Memory

  • 4 GB x32 LPDDR4-1600 for MSS
  • 1 GB x16 LPDDR3-1333 for FPGA logic

• Storage

  • 2 x 16 GB eMMC 5.1 (higher capacities also possible)
  • 1 Gb NOR flash (standard)
  • microSD card via SPI bus (shared with PC/104+)
  • I²C EEPROM for saving board parameters

• Networking

  • 2 x SFP+ connectors for 1/10 Gbps Ethernet with load switch to manage SFP power
  • 2 x RJ45 connectors for 10/100/1000 Mbps Ethernet
  • 1 x USB OTG with around 1A current sourcing limit via USB power switch

• PCIe Gen 2 (5GT/s)

  • Full bandwidth (4 Gbps) between any two boards in cluster via USB Type-C
  • One board working as PCIe root can serve up to five boards in EP mode for a total of six boards in a cluster

• Clock

  • I²C programmable SiLabs Si5332H-D-GM3 clock generator (external oscillator option also supported)
  • MAX31342 real-time clock (RTC) support and 32.768 KHz clock generation
  • 2 x spare LVDS programmable clock pairs connected to BANK1 of SoC in addition to required reference clocks

• Shared resources on up to six-board stackable cluster with PC/104+ connector

  • Power & ground
  • SPI (shared with microSD connector), I²C (buffered), 6 x GPIO
  • Common cluster reset (CCR) for up to six boards in a cluster
  • 1 x programmable LVDS clock
  • Polarfire SoC Probe_P&N (any signal up to 100 MHz inside the SoC can be routed for test purposes)

• Power

  • 12 VDC / 7 A maximum screw terminal connector
  • Fanless operation with < 20 W for full configuration with 2 x 10 Gbps SFP+
  • Multiple supplies (nominal 12 VDC or 15 VDC) can be used for power redundancy
  • Each board in cluster has own power protection and filtering
  • 20 mm SMT coin cell battery holder for real-time clock
  • 2 x 5 VDC header

• Status LEDs right-angle header

  • Power-on
  • Reset
  • Alarm
  • Ethernet
  • Root/EP
  • PCIe link
  • User LEDs via LED board connected to the right angle header

• Reset push-buttons with onboard supervisor

  • Board reset
  • Common cluster reset (CCR)

• Debug

  • 1 x USB 2.0 micro Type-B receptacle for USB-UART
  • Watchdog timer
  • JTAG header

• Dimensions

  • Approximately 18 cm x 12 cm x 2 cm
  • Weight TBD

Comparisons

Microchip’s PolarFire SoC is just now becoming available. How does SAVVY-V differ from the Icicle Kit and PolarBerry, which use the same SoC? SAVVY-V has more DDR memory (4 GB for LPDDR4 rather than 2 GB, and additional LPDDR3 for FPGA logic), more storage (up to for eMMC 5.1), and high-speed (5 GT/s or 4 Gbps) USB Type-C to connect between SAVVY-V or expansion boards. Of course, SAVVY-V will be correspondingly more expensive as well, though I don’t know the exact pricing yet due to the fact Polarfire SoC pricing is not yet publicly available. Moreover, some custom requests on memory capacity and SoC logic density (25K, 95K, 160K, or 250K logic elements) and speed (standard or 15% faster -1 speed grade) will have different pricing.

Block Diagram

Stay in Touch

As I make progress on the board design and eventually make and test prototypes, I’ll post updates on this page. You can subscribe to updates by clicking the big button at the top of the page. You can also get in touch with me directly, and I encourage you to check out the Flexible Open Source Hardware for RISC-V (FOSOH-V) LinkedIn group I created.