Answering most frequently asked questions about a carrier board design for XTRX:

1. Max height from carrier PCB includes XTRX components in C.S.

It depends of the connector type of carrier board, but not XTRX.
In according to miniPCIe standard, thickness of the component layer on the bottom side of the XTRX board itself is 1 mm maximum.
We use 1.55 mm gap connector MM60-52B1-G1-R850 with stand off NT1R3000, so thermal pad (gap filler) to carrier PCB would be ~0.8 mm like H48-6G-50-10-0.8-1A. 2. Do you use USB2 port on the miniPCIe slot?
No. We use PCIe lane(s) to communicate. 3. How do you download bitstream into FPGA?
We’re planing to implement software re-flashing to make update procedure seamless for users. Right now this function is not ready yet, so we’re using JTAG (see pinout for spring contacts at the XTXR Connectors Pinout). When software re-flashing is implemented, JTAG will only be needed for FPGA development. 4. Do you need I2C bus connection? If yes which I2C address is being used?
We don’t use I2C 5. Do you use WLAN LEDs?
Yes. All LEDs are connected to the FPGA and can be configured in software. 6. Do you use PCIe-WAKE# signal?
No 7. Do you need 39,41 pins? We may need them for our own purpose.
We use these pins for the second PCIe lane. The XTRX board has 0-ohm resistor on the second lane, so you can disable it by unsoldering these resistors. 8. Do you use 1.5 V? if yes do you need some 3.3 V -> 1.5 V sequence?
We don’t use 1.5 V. 9. Do you use 3.3 VAUX? if yes do you need some 3.3 V → 3.3 VAUX sequence?
We don’t use 3.3 VAUX. 10. Which reserved pins do you use for RF clock synchronization? Is it possible to synchronize XTRX from external 10 MHz clock or 1PPS? If yes, which pin numbers are used?
Yes, you can use 1PPSI_GPIO1 for 1PPS in and MHZ_IN for input reference clock. 10 MHz to 52 MHz reference clock frequencies should work fine (we need to test frequencies > 32 MHz to be 100% sure, but we expect them to work).